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The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores project.

A large number of open-source designs for CPUs, and auxiliary computer peripherals have now been released with Wishbone interfaces. Many can be found at OpenCores, a foundation that attempts to make open-source hardware designs available.

Wishbone is intended to be a "logic bus." It does not specify electrical information or the bus topology. Instead, the specification is written in terms of "signals", clock cycles, and high and low levels.

This ambiguity is intentional. Wishbone is made to let designers combine several designs written in Verilog, VHDL or some other logic-description language for electronic design automation. Wishbone provides a standard way for these hardware logic designs (called "cores") to be combined. Wishbone is defined to have 8, 16, 32, and 64-bit buses. All signals are synchronous to a single clock but some slave responses must be generated combinatorially for maximum performance. Wishbone permits addition of a "tag bus" to describe the data, but reset, simple addressed reads and writes, movement of blocks of data, and indivisible bus cycles all work without tags.

Wishbone is open source in order to make it easy for engineers and hobbyists to share public domain designs for hardware logic on the Internet. In order to prevent preemption of its technologies by aggressive patenting, the Wishbone spec includes examples of preexisting art, to prove that its concepts are in the public domain.

A device does not "conform" to the Wishbone spec unless it includes a "data sheet" that describes what it does, bus width, utilization, etc. The data sheet is required in order to promote reuse of a design. Making a design reusable in turn makes it easier to share with others.

Contents 1 Wishbone Topologies 1.1 Shared Bus 1.2 Pipeline 1.3 Cross Bar Switch 2 Comparisons 3 Competitors 4 External links

Wishbone adapts well to common topologies such as point-to-point, many-to-many (i.e. the classic bus system), hierarchical, or even switched fabrics such as crossbar switches. In the more exotic topologies, Wishbone requires a bus controller or

Wishbone Control Signals Compared to Other SOC Bus Standards

Wishbone => Avalon

Wishbone	Avalon Bus	Description
cyc	= chipselect	indicates that a valid bus cycle is in progress
stb	= !write_n or !read_n	indicates a valid data transfer cycle
we	= !write_n and read_n	indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles.
ack	= !waitrequest	indicates the termination of a normal bus cycle by slave device.

Avalon => Wishbone

Avalon Bus	Wishbone	Description
chipselect	= cyc	indiates that slave device is selected.
write_n	= !(stb and we)	indicated that master requests to read from slave device.
read_n	= !(stb and !we)	indicated that master requests to read from slave device.
waitrequest	= !ack	indicates that slave requests that master wait.

• Avalon Bus
• AMBA bus / AHB (AMBA High-Speed Bus)
• PLB Processor local Bus
• OCP Open Core Protocol
• OPB On-chip Peripheral Bus

• Wishbone Version B3- the PDF specification
• Wishbone Bus project page
• Opencores
• Wishbone To AHB project page - Wishbone to AHB bridge